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? november 2003 1/17 vnd830asp double channel high side solid state relay (*) per channel n dc short circuit current: 6a n cmos compatible inputs n proportional load current sense n undervoltage and overvoltage shut-down n overvoltage clamp n thermal shut-down n current limitation n very low stand-by power dissipation n protection against: loss of ground and loss of v cc n reverse battery protection (**) description the vnd830asp is a monolithic device made using stmicroelectronics vipower m0-3 technology. it is intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). this device has two channels in high side configuration; each channel has an analog sense output on which the sensing current is proportional (according to a known ratio) to the corresponding load current. built-in thermal shut-down and outputs current limitation protect the chip from over temperature and short circuit. device turns off in case of ground pin disconnection. type r ds(on) i out v cc vnd830asp 60 m w (*) 6 a (*) 36 v (*) 1 10 powerso-10 ? order codes package tube t&r powerso-10 ? vnd830asp VND830ASP13TR logic undervoltage overvoltage overtemp. 1 overtemp. 2 i lim2 pwclamp 2 k i out2 i lim1 pwclamp 1 k i out1 input 1 input 2 gnd v cc output 1 current sense 1 output 2 current sense 2 driver 2 driver 1 v cc clamp ot1 ot2 ot1 ot2 v dslim1 v dslim2 block diagram (**) see application schematic at page 8
2/17 vnd830asp absolute maximum rating connection diagram (top view) symbol parameter value unit v cc dc supply voltage 41 v -v cc reverse supply voltage - 0.3 v -i gnd dc reverse ground pin current - 200 ma i out output current internally limited a i r reverse output current - 6 a i in input current +/- 10 ma v csense current sense maximum voltage -3 +15 v v v esd electrostatic discharge (human body model: r=1.5 w ; c=100pf) - input - current sense - output - v cc 4000 2000 5000 5000 v v v v e max maximum switching energy (l=1.8mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =9a) 100 mj p tot power dissipation at t c =25c 74 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c current and voltage conventions 1 2 3 4 5 6 7 8 9 10 11 output 2 output 2 n.c. output 1 output 1 ground input2 input1 c.sense1 c.sense2 v cc i s i gnd output2 v cc i out2 v cc v sense2 current sense 1 i sense1 v out2 output1 i out1 current sense 2 i sense2 v sense1 v out1 input2 i in2 input1 i in1 v in2 v in1 ground
3/17 vnd830asp thermal data (*) when mounted on a standard single-sided fr-4 board with 0.5cm 2 of cu (at least 35 m m thick). horizontal mounting and no artificial air flow electrical characteristics (8v 4/17 vnd830asp electrical characteristics (continued) v cc - output diode protections current sense (9v v cc 16v) (see figure 1) note 2: current sense signal delay after positive input slope. note: sense pin doesnt have to be left floating. symbol parameter test conditions min typ max unit v f forward on voltage -i out =2a; t j =150c 0.6 v symbol parameter test conditions min typ max unit i lim current limitation vcc=13v 5.5v8v, i out1,2 =2.5a; r sense =10k w 2 4 v v v senseh sense voltage in overtemperature conditions v cc =13v; r sense =3.9k w 5.5 v r vsenseh analog sense output impedance in overtemperature condition v cc =13v; tj>t tsd ; all channels open 400 w t dsense current sense delay response to 90% i sense (see note 2) 500 m s
5/17 vnd830asp truth table (per channel) electrical transient requirements conditions input output sense normal operation l h l h 0 nominal overtemperature l h l l 0 v senseh undervoltage l h l l 0 0 overvoltage l h l l 0 0 short circuit to gnd l h h l l l 0 (t j t tsd ) v senseh short circuit to v cc l h h h 0 < nominal negative output voltage clamp ll 0 iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 w 2 +25 v +50 v +75 v +100 v 0.2 ms 10 w 3a -25 v -50 v -100 v -150 v 0.1 m s 50 w 3b +25 v +50 v +75 v +100 v 0.1 m s 50 w 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 w 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 w iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5c e e e class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
6/17 vnd830asp figure 1: i out /i sense versus i out figure 2: switching characteristics (resistive load r l =6.5 w ) v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) i sense t t 90% t d(off) input t 90% t d(on) t dsense 0 0.5 1 1.5 2 2.5 3 iout (a) 500 750 1000 1250 1500 1750 2000 2250 iout/isense typical value max tj= -40oc min tj= -40oc max tj=25...150oc min tj=25...150oc
7/17 vnd830asp figure 3: waveforms sense n input n normal operation undervoltage v cc v usd v usdhyst input n overvoltage v cc sense n input n sense n load current n load current n load current n v ov v cc > v ov v cc < v ov short to ground input n load current n sense n load voltage n overtemperature input n sense n t tsd t r t j load current n input n load voltage n sense n load current n 8/17 vnd830asp gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / i s(on)max . 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsds. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input thresholds and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input line is also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input pin is to leave it unconnected, while unused sense pin has to be connected to ground pin. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. v cc gnd output2 current sense1 d ld +5v r prot r sense2 output1 r sense1 input1 d gnd r gnd v gnd current sense2 input2 m c r prot r prot r prot application schematic
9/17 vnd830asp m c i/os protection: if a ground protection network is used and negative transient are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 65k w . recommended r prot value is 10k w.
10/17 vnd830asp high level input current input clamp voltage off state output current -50 -25 0 25 50 75 100 125 150 175 tc (oc) 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma input high level -50 -25 0 25 50 75 100 125 150 175 tc (oc) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) vcc=13v input hysteresis voltage input low level -50 -25 0 25 50 75 100 125 150 175 tc (oc) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 1 2 3 4 5 6 7 8 il(off1) (ua) off state vcc=13v vin=vout=0v
11/17 vnd830asp overvoltage shutdown turn-on voltage slope turn-off voltage slope i lim vs t case -50 -25 0 25 50 75 100 125 150 175 tc ( oc) 30 32.5 35 37.5 40 42.5 45 47.5 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (o c) 200 250 300 350 400 450 500 550 600 dvout/dt(on) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc (o c) 0 50 100 150 200 250 300 350 400 450 500 dvout/dt(off) (v/ms) vcc=13v rl=6.5ohm on state resistance vs t case on state resistance vs v cc -50 -25 0 25 50 75 100 125 150 175 tc ( oc) 0 2.5 5 7.5 10 12.5 15 17.5 20 ilim (a) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 10 20 30 40 50 60 70 80 90 100 ron (mohm) iout=5a vcc=8v & 36v 5 10152025303540 vcc (v) 20 30 40 50 60 70 80 90 100 ron (mohm) iout=5a tc=150oc tc=25oc tc= -40oc
12/17 vnd830asp maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 1 10 100 0.1 1 10 100 l(mh) i lmax (a) a b c
13/17 vnd830asp powerso-10 ? pc board r thj-amb vs pcb copper area in open box free air condition powerso-10 ? thermal data layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: from minimum pad lay-out to 8cm 2 ). 30 35 40 45 50 55 0246810 pcb cu heatsink area (cm^2) rthj_amb (c/w) tj-tamb=50c
14/17 vnd830asp thermal fitting model of a double channel hsd in powerso-10 pulse calculation formula thermal parameter area/island (cm 2 )0.56 r1 (c/w) 0.15 r2 (c/w) 0.8 r3( c/w) 0.7 r4 (c/w) 0.8 r5 (c/w) 12 r6 (c/w) 37 22 c1 (w.s/c) 0.0006 c2 (w.s/c) 2.10e-03 c3 (w.s/c) 0.013 c4 (w.s/c) 0.3 c5 (w.s/c) 0.75 c6 (w.s/c) 3 5 z th d r th d z thtp 1 d C () + = where d t p t = powerso-10 thermal impedance junction ambient single pulse t_amb pd1 c1 r4 c3 c4 r3 r1 r6 r5 r2 c5 c6 c2 pd2 r2 c1 c2 r1 tj_1 tj_2 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zt h (c/w) 0.5 cm 2 6 cm 2
15/17 vnd830asp dim. mm. inch min. typ max. min. typ. max. a 3.35 3.65 0.132 0.144 a (*) 3.4 3.6 0.134 0.142 a1 0.00 0.10 0.000 0.004 b 0.40 0.60 0.016 0.024 b (*) 0.37 0.53 0.014 0.021 c 0.35 0.55 0.013 0.022 c (*) 0.23 0.32 0.009 0.0126 d 9.40 9.60 0.370 0.378 d1 7.40 7.60 0.291 0.300 e 9.30 9.50 0.366 0.374 e2 7.20 7.60 0.283 300 e2 (*) 7.30 7.50 0.287 0.295 e4 5.90 6.10 0.232 0.240 e4 (*) 5.90 6.30 0.232 0.248 e 1.27 0.050 f 1.25 1.35 0.049 0.053 f (*) 1.20 1.40 0.047 0.055 h 13.80 14.40 0.543 0.567 h (*) 13.85 14.35 0.545 0.565 h 0.50 0.002 l 1.20 1.80 0.047 0.070 l (*) 0.80 1.10 0.031 0.043 a 0o 8o 0o 8o a (*) 2o 8o 2o 8o powerso-10 ? mechanical data (*) muar only poa p013p detail "a" plane seating a l a1 f a1 h a d d1 = = = = e4 0.10 a c a b b detail "a" seating plane e2 10 1 eb he 0.25 p095a
16/17 vnd830asp powerso-10 ? suggested pad layout 1 tape and reel shipment (suffix 13tr) reel dimensions all dimensions are in mm. base q.ty 600 bulk q.ty 600 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed 6.30 10.8 - 11 14.6 - 14.9 9.5 1 2 3 4 5 1.27 0.67 - 0.73 0. 54 - 0.6 10 9 8 7 6 b a c all dimensions are in mm. base q.ty bulk q.ty tube length ( 0.5) a b c ( 0.1) casablanca 50 1000 532 10.4 16.4 0.8 muar 50 1000 532 4.9 17.2 0.8 tube shipment (no suffix) c a b muar casablanca
17/17 vnd830asp information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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